> Thought I'd "close the loop" on my experience with the MOSFET booster circuit.
Great - thanks for the follow-up, I was hoping to hear more about it and see if I needed to revisit the circuit plan. Sorry you lost some chips in the process!
> Having said that the numbers don't quite stack up using a simple Ohms Law calculation,
> but the real-life experimentation doesn't lie.
Indeed, experimentation has a ruthless tendency to take into account all of the details one misses or hand-waves away when doing it on paper.
But I'd really like to figure out what I'm missing in the analysis. Let me go through my thinking in a little more detail, see if you have any insights about what I'm getting wrong.
> I did note on the specification sheet under Absolute Maximum Ratings that while rated to 5A,
> that is for 0.5uS whereas the I OUT_DC (output continuous source / sink current) is 0.3A Max.
Quite so. BUT! This is a MOSFET gate we're talking about:
Sorry for the crude hand sketch, but what I'm trying to show is a test circuit that measures the steady-state current from the 12V supply into the gate - the DC continuous output source/sink current from the data sheet, with the 300mA absolute maximum. "A" is the ammeter. If we turn the power on and leave it on, what will the ammeter read? It's not an Ohm's law thing where we're going to read 12V/1R = 1A. It's a MOSFET gate, so we're going to see a nice round 0 on the ammeter. A little blip when we first apply power, but then 0 for as long as we leave it on.
More dynamically, the current is going to follow a curve like this when you first turn on the power:
When voltage is initially applied, current flows as fast as the gate resistor allows it to. But the current just goes into charging up the gate, so as charge accumulates on the gate, the current slows down on an exponential decay curve, ultimately flatlining at zero once the gate is fully charged. I'm oversimplifying - there's that whole Miller plateau business - but to a first approximation, you get a brief surge of current, quickly tapering off to zero as the gate charges.
There's a corresponding negative current surge when the power turns off, because the gate driver chip is deliberately designed to short the gate straight to ground when the drive turns off, to discharge the gate as fast as it charged the gate on the way in. So for PWM drive, it looks like:
So the implication seems to be that these pulses at the PWM switching points are exceeding the 0.5us allowance we have
> They seem to be OK until you run them on a higher duty cycle, ie setup as digital out or PWM > 240 out of 255.
That does make some sense to me - and there should be a corresponding danger zone at the low end. It's not the 255 that's the problem, it's the ALMOST 255, and correspondingly, ALMOST 0. Those ought to be the zones of maximum danger exactly because of the surge of current at the ON and OFF edges of the input signal. When the PWM cycle is ALMOST 100%, it spends almost the whole PWM period ON, turns OFF briefly near the end of the period, and then turns right back ON. So you get a gate discharge interval leading straight into a gate charge interval, back to back, without any break in between for the poor driver chip:
And the mirror image for duty cycle near 0%: you get a charge interval leading straight into a discharge interval:
The negative discharge current places the same power dissipation demands on the driver chip as the positive charge current, so having them back to back essentially doubles the "pulse" interval.
> I am using an IRF540N N-Channel MOSFET
That's probably the difference between our test setups that made me think 4.7R was safe. I'm using BUK7K89-100E. Comparing data sheets, IRF540N has a much higher gate charge than BUKetc, so the time spent in the high-current charging/discharging zone is going to be correspondingly longer.
To an extremely rough first approximation, the high-current pulse time is Q[gd]/I, where I is the current. That should be fairly ohmic during the Miller region, at (V[supply] - V[G][th])/R[g]. For your chip, V[G][th] is about 4V and Q[gd] is 13nC, so with 12V supply and 4.7R, we get I=1.7A, and pulse time 7.6ns. That's still a tiny fraction of the 0.5us allowance in the data sheet.. But it's higher than my BUKetc, where I get 2.8ns by the same method. For the "almost 0%" and "almost 100%" PWM scenarios we've been talking about, we can double those to 15.2ns and 5.6ns - but still way less than 500ns.
Are you running PWM at 20 kHz? That's a 50us period, so that's eons for the chip to cool off between cycles. Huh, I still do not get it. 15.2ns of current over 50us is only 0.03% duty cycle. I was expecting to arrive at a realization here that the pulse time was saturating the PWM cycle, giving the driver chip too little time to cool off between pulses. But unless you've running your PWM in the MHz range, that doesn't seem to be it either.
I'm going to have to go back the data sheet and see what I can find. Do let me know if you see any errors in my math.
At any rate, your finding that 150R is the cutoff point for safe operation is a good empirical result. That limits the pulse current to 80mA, which is well within the 0.3A DC allowance. I don't suppose you have an oscilloscope you can hook up to see what the actual empirical charge/discharge times are like for the 620R you settled on? Back-of-the-envelope (same calculations as above) say that should give you about 1us turn on/turn off times, which is still only 4% (total) of the 50us PWM period at 20 kHz. I.e., the MOSFET is only going to spend 4% of its time in the region where it tends to heat up. That's easy enough to empirically test as well, just hook up a big motor or something and run it at various PWM levels to see if the MOSFET gets hot.
Edited by mjr, 21 February 2025 - 08:19 AM.
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